Method for forming dual inlaid structures for ic interconnections

Abstract

A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The first dielectric layer, middle stop layer, second dielectric layer and cap layer are then deposited over both regions and two via openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via formation. A trench pattern is then defined in the second dielectric layer and the etch stop layers are then removed in the openings and a conductive material is formed therein.