The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Dec. 03, 2002
Applicant:
Inventors:

Scott R. Summerfelt, Garland, TX (US);

Tomohuki Sakoda, Yamanashi, JP;

Chiu Chi, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/162 ;
U.S. Cl.
CPC ...
H01L 2/162 ;
Abstract

The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.


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