The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2004
Filed:
Dec. 28, 2000
Applicant:
Inventors:
Gustavo P. Espinosa, Portland, OR (US);
Meera Agrawal, Mountain View, CA (US);
Kjeld Svendsen, Santa Clara, CA (US);
Bryan C. Tipton, San Diego, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/24 ; G06F 1/576 ;
U.S. Cl.
CPC ...
G06F 1/24 ; G06F 1/576 ;
Abstract
A method and system provides for changing processor configuration during operation of the processor system. The method and system include a control logic circuit where the control logic circuit sets a control bit to change the size of a processor array that allows disabling (defeaturing) of at least a portion of the array and enabling of a different performance operating mode for the processor system.
Espinosa, Gustavo. (2004). Method and apparatus for dynamic processor configuration by limiting a processor array pointer (U.S. Patent No. 6766449). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6766449
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