Clock tree synthesizer for balancing reconvergent and crossover clock trees

Abstract

A clock tree synthesizer alters a clock tree design to balance a clock tree receiving and distributing one or more clock signals to many clocked devices (“sinks”) within an integrated circuit, wherein the clock tree includes one or more crossover and reconvergence points at outputs of multiplexers receiving clock signals via different paths through the clock tree. The clock tree synthesizer balances the clock tree by first balancing the subtree downstream of each multiplexer and then representing the multiplexer and the subtree with a separate macro for each multiplexer input, each macro representing the path delay from the corresponding multiplexer input to the sinks receiving clock signal inputs via the subtree. When the clock tree includes crossover points, the macros split the clock tree into a separate tree for each clock signal. The clock tree synthesizer then balances each resulting separate tree, and thereafter replaces the macros with the multiplexers and balanced subtrees they represent, thereby producing a single balanced clock tree for all of the distributed clock signals.