The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2004

Filed:

Jan. 18, 2000
Applicant:
Inventors:

Maria Clemens Y. Quinones, Cebu, PH;

Gilmore S. Baje, Lapulapu, PH;

Maria Christina B. Estacio, Cebu, PH;

Marvin R. Gestole, Lapulapu, PH;

Oliver M. Ledon, Lapulapu, PH;

Santos E. Mepieza, Mandaue, PH;

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/148 ; H01R 4/300 ;
U.S. Cl.
CPC ...
H01L 2/148 ; H01R 4/300 ;
Abstract

A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies therebetween and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.


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