The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2004
Filed:
May. 16, 2001
James S. Ledford, Cedar Park, TX (US);
Alex S. Yap, New York, NY (US);
Robert A. Jensen, Austin, TX (US);
Brian E. Cook, Austin, TX (US);
Mark S. Aurora, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit has a Built-In Self-Test (BIST) controller ( ) that has a sequencer ( ) that provides test algorithm information for multiple memories ( ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. This timing information is read prior to performing the test algorithm and is used in performing the test algorithm.