The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2004

Filed:

Jun. 18, 2002
Applicant:
Inventors:

Thomas Skotnicki, Crolles-Montfort, FR;

Alexandre Villaret, Grenoble, FR;

Assignee:

STMicroelectronics SA, Montrouge, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/714 ;
U.S. Cl.
CPC ...
H01L 2/714 ;
Abstract

An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.


Find Patent Forward Citations

Loading…