The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2004

Filed:

Nov. 07, 2002
Applicant:
Inventors:

Jian-Hsing Lee, Hsin-Chu, TW;

Ta-Lee Yu, Hsin-Chu, TW;

Shui-Hung Chen, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/362 ;
Abstract

In a high voltage n-channel MOS structure, inserting p+ diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.


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Lee, Jian-Hsing. (2004). Integrated circuit having improved esd protection (U.S. Patent No. 6756642). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6756642

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