The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2004
Filed:
Jun. 29, 2001
Steven R. Bristow, San Jose, CA (US);
Paul Magliocco, Los Gatos, CA (US);
Seth W. Craighead, San Jose, CA (US);
Nextest Systems Corporation, San Jose, CA (US);
Abstract
A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus ( ) includes: (i) pin electronics (P/Es ) each coupling the apparatus to one of a number of pins ( ) on device ( ); (ii) timing and format circuits (T/Fs ) for mapping a signal to one of P/Es ( ); (iii) pattern generator ( ) having a number of outputs for outputting signals for testing device ( ); (iv) pin scrambling circuit ( ) between pattern generator ( ) and T/Fs ( ), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock ( ) for providing a clock signal having a clock cycle to pattern generator ( ) and T/Fs ( ). T/Fs ( ) are capable of switching the signals coupled to P/Es ( ) at least twice each clock cycle.