The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2004
Filed:
Dec. 28, 2000
Ajay Ojha, Beaverton, OR (US);
Hehching Harry Li, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A novel apparatus and methods provide the capability to structural test device input/output pins which are not connected to an external tester during the testing process. The method does not require a new Design For Test logic block, but rather, the method modifies existing registers on the chip to function as a (Pseudo Random Pattern Generator) PRPG and a MISR (Multiple Input Signature Register). The PRPG generates input patterns. The MISR generates an output signature. PRPG and MISR are both based on LFSR (Linear Feedback Shift Register). This allows running a random pattern generated by the PRPG, testing at-speed a path from the PRPG through the I/O logic circuitry interfacing to core logic, and storing a signature pattern in the MISR. The testing will take place at native speed of the device and no connection to the pins is required externally.