The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2004
Filed:
Nov. 12, 2002
Gwo-Shii Yang, Hsinchu, TW;
Jen Kon Chen, Hsin-Chu, TW;
Hsueh-Chung Chen, Yunghe, TW;
Hans-Joachim Barth, Munich, DE;
Chiung-Sheng Hsiung, Kaohsiung, TW;
Chih-Chien Liu, Taipei, TW;
Tong-Yu Chen, Hsinchu, TW;
Yi-hsiung Lin, Wappingers Falls, NY (US);
Chih-Chao Yang, Beacon, NY (US);
Infineon Technologies AG, Munich, DE;
Abstract
A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.