Efficient system bus architecture for memory and register transfers

Abstract

A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines in which upon the falling edge of the grant signal from the memory controller for a first memory transaction and prior to the completion of the servicing of the first memory transaction, a second memory transaction can be issued. Once a first address corresponding to the first memory transaction request is transmitted to the memory controller, the address lines are available for transmitting a second address corresponding to the second memory transaction request to the memory controller. The memory controller then stores the second address in a buffer whereupon the completion of servicing the first memory transaction request, the second request can be serviced without waiting for the second request arbitration process or for the address to be transmitted to the memory controller. In addition, in another aspect of the method for efficiently utilizing the system bus, register transactions between system sub-blocks and the system's central processing unit are performed using the system bus by multiplexing register data onto the address signal lines of the system bus when the address signal lines are idle, thereby further minimizing address line idle cycles.