The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Feb. 27, 2002
Yukiko Umemoto, Kodaira, JP;
Toshihiro Tanaka, Akiruno, JP;
Hiroyuki Tanikawa, Kodaira, JP;
Yutaka Shinagawa, Iruma, JP;
Other;
Abstract
This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC among flash memory cells MC to MC formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL in which the memory cell MC is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL . As a result, parasitic capacitances Ca and Ca generated between p type wells PWL and PWL in which the unselected memory cells MC and MC are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.