The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Aug. 09, 2001
Alan H. Kramer, Berkeley, CA (US);
Danielle A. Thomas, Dallas, TX (US);
STMicroelectronics, Inc., Carrollton, TX (US);
Abstract
Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.