The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2004
Filed:
Jul. 09, 2001
David W. Chrudimsky, Austin, TX (US);
Stephen C. Horne, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Michael R. Seningen, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
A method and apparatus for random-access scan of a network of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates ( ) driven by multiple overlapping clock signals generated from a clock generation circuit ( ) coupled to a clock spine ( ). Each clocked precharge logic gate and each scan gate include a logic tree ( ) with one or more evaluate nodes, a precharge circuit ( ), an evaluate circuit ( ), and one or more output buffers ( ). Each scan gate further includes a scan circuit ( ) that accepts scan control signals ( , and ) and couples to one or more scan registers ( ) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.