Semiconductor device manufacturing method

Abstract

It is an object to provide a technique for reducing an electric resistance between a contact plug and an impurity region to be electrically connected thereto while maintaining an insulating property between a gate electrode and the contact plug. A sidewall insulating film ( ) is formed on a side surface of a gate structure ( ) provided on a semiconductor substrate ( ), and epitaxial layers ( ) and ( ) are formed in self-alignment on n-type impurity regions ( ) and ( ) so that the sidewall insulating film ( ) lies between the epitaxial layers ( ) and ( ) and a gate electrode ( ). An etching blocking film ( ) and an interlayer insulating film ( ) are formed over a whole surface in this order. Using the etching blocking film ( ) as an etching stopper, the interlayer insulating film ( ) is etched and the exposed etching blocking film ( ) is subsequently etched. Consequently, contact holes ( ) and ( ) reaching the epitaxial layers ( ) and ( ) are formed.