The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2004

Filed:

Mar. 29, 2002
Applicant:
Inventors:

Jiri L. Vasat, Chesterfield, MO (US);

Andrei Stefanescu, O'Fallon, MO (US);

Thomas A. Torack, Oakland, MO (US);

Gregory M. Wilson, Chesterfield, MO (US);

Assignee:

MEMC Electronic Materials, Inc., St. Peters, MO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/906 ; H01L 2/701 ;
U.S. Cl.
CPC ...
H01L 2/906 ; H01L 2/701 ;
Abstract

A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100° C. by exposing the front surface to a cleaning ambient comprising H , HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100° C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.


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