The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2004

Filed:

Oct. 04, 2002
Applicant:
Inventors:

Daran DeShazo, Dallas, TX (US);

Agustinus Sutandi, Murphy, TX (US);

Jason Stevens, Plano, TX (US);

Assignee:

HPL Technologies, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/600 ;
U.S. Cl.
CPC ...
G11C 1/600 ;
Abstract

An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.


Find Patent Forward Citations

DeShazo, Daran. (2004). One-time-programmable bit cell with latch circuit having selectively programmable floating gate transistors (U.S. Patent No. 6741500). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6741500

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…