The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2004

Filed:

Mar. 08, 2002
Applicant:
Inventors:

Jong-Hwan Kim, Bucheon, KR;

Cheol-Joong Kim, Bucheon, KR;

Suk-Kyun Lee, Bucheon, KR;

Yongcheol Choi, Shiheung, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18258 ;
U.S. Cl.
CPC ...
H01L 2/18258 ;
Abstract

A semiconductor device and a method of manufacturing the semiconductor device having a vertical NPN bipolar transistor, a lateral PNP bipolar transistor, and P-type and N-type resistors are disclosed. In one embodiment, a photoresist pattern is formed on a pad oxide layer and field oxides on an N-type epitaxial layer that is grown on a P-type semiconductor substrate. The pad oxide layer is etched after implanting P-type impurity into the epitaxial layer by using the photoresist pattern as a mask. Deposition of a polysilicon layer after removing the photoresist pattern is followed by implanting P-type impurity and N-type impurity into the polysilicon layer in sequence. Another photoresist pattern formed on the polysilicon layer after the previous implantation is used as an etch mask for etching the polysilicon layer to form polysilicon electrodes of transistors and P-type and N-type resistors as well as expose the surface of the epitaxial layer near an emitter region of the vertical transistor. P-type impurity is implanted into the epitaxial layer through the exposed surface thereof by using the photoresist pattern as an implant mask. The structure is then subjected to heat treatment to form emitter, intrinsic and extrinsic base, and collector regions of the transistors.


Find Patent Forward Citations

Loading…