The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2004

Filed:

Mar. 22, 2001
Applicant:
Inventors:

Terrence J. Riley, Austin, TX (US);

Qingsu Wang, Austin, TX (US);

Glen W. Scheid, Gresham, OR (US);

Kent F. Knox, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/126 ;
U.S. Cl.
CPC ...
G01R 3/126 ;
Abstract

A method for identifying faulty wafers includes processing a set of wafers in a tool; collecting tool state information during the processing of the set of wafers; generating a tool state information baseline; comparing the tool state information for each wafer to the tool state information baseline to identify any wafers with outlying tool state information; and designating a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer. A processing line includes a tool adapted to process a set of wafers, and a process controller. The process controller is adapted to collect tool state information during the processing of the set of wafers, generate a tool state information baseline, compare the tool state information for each wafer to the baseline tool state information to identify any wafers with outlying tool state information, and designate a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer.


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