The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2004
Filed:
Dec. 10, 2002
Applicant:
Inventors:
Assignee:
Texas Insturments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/13205 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/13205 ; H01L 2/1336 ;
Abstract
The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer ( ) on top of a native oxide layer above a silicide layer ( ) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer ( ) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.