The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2004

Filed:

Nov. 15, 2002
Applicant:
Inventors:

Chrong Jung Lin, Hsin-Tian, TW;

Shui-Hung Chen, Hsin-Chu, TW;

Hsin-Ming Chen, Hsin-Ying, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.


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