The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2004
Filed:
May. 24, 2002
Stephen C. Horne, Austin, TX (US);
Gopal Vijayan, Austin, TX (US);
Donald W. Glowka, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
This invention discloses a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool includes a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool . The routing rule generation tool further includes a noise sensitivity/gate characterization tool and a rule generator tool . The block build tool further includes a gate sizing tool , a gate analysis tool , a route rule selecting tool , a route assigning tool