The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2004
Filed:
Nov. 12, 2002
Applicant:
Inventors:
Shatil Haque, Mohegan Lake, NY (US);
Gert Bruning, Sleepy Hollow, NY (US);
Assignee:
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/304 ;
U.S. Cl.
CPC ...
H01L 2/304 ;
Abstract
A multichip wirebond-less integrated circuit and power die package is based on a folded single-layer flex circuit. The package is formed with metal-studbumped power dies and IC's flipchiped to a patterned flex substrate. Extensions of the flex substrate are folded and attached to the backside of the dies for electrical and/or thermal contact. I/O pins are along the periphery of the package for standard SMT mounting while heatspreaders are attached to both sides of the package for double-sided cooling.