The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2004

Filed:

May. 05, 2000
Applicant:
Inventor:

Hisashi Nakamura, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1/540 ;
U.S. Cl.
CPC ...
G06T 1/540 ;
Abstract

In a frame buffer memory including a DRAM ( ), an SRAM ( ) functioning as a cache memory, and a comparison unit ( ) comparing depth data stored in the SRAM ( ) and depth data input from an external source and writing depth data input from the external source directly to the SRAM ( ) when depth data input from the external source represents a shallower point on a screen, a maxZ detection circuit ( ) detecting depth data representing a deepest point among depth data of eight pixels stored in each memory block ( ) of SRAM ( ) is provided. The detection circuit ( ) does not compare depth data of each pixel as comparison unit ( ) but detects depth data representing a deepest point among depth data of eight pixels, whereby a Z buffering process is sped up.


Find Patent Forward Citations

Nakamura, Hisashi. (2004). Semiconductor integrated circuit device (U.S. Patent No. 6727900). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6727900

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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