The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6727186 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 27, 2004

Filed:

Apr. 15, 2002
Applicant:
Inventors:

Thomas Skotnicki, Crolles, FR;

Malgorzata Jurczak, Grenoble, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.


Find Patent Forward Citations

Skotnicki, Thomas. (2004). Method for lateral etching with holes for making semiconductor devices (U.S. Patent No. 6727186). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6727186

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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