The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Apr. 22, 2002
Applicant:
Inventors:

Tsutomu Nagasawa, Hyogo, JP;

Hideki Yonetani, Hyogo, JP;

Kozo Ishida, Hyogo, JP;

Shinichi Jinbo, Hyogo, JP;

Makoto Suwa, Hyogo, JP;

Tadaaki Yamauchi, Hyogo, JP;

Junko Matsumoto, Hyogo, JP;

Zengcheng Tian, Hyogo, JP;

Takeo Okamoto, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.


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