The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Jan. 14, 2003
Atsushi Yoshikawa, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers ( ) to a clock propagation control gate ( ). The two-level clock propagation control gate ( ) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate ( ) propagates through buffers ( ) to reach a sequential circuit ( ) at an end point. The NAND gate ( ) at the second level of the clock propagation control gate ( ) includes nMOS transistors ( ) and pMOS transistors ( ). The inverter ( ) at the first level includes a pMOS transistor ( ) and an nMOS transistor ( ).