The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Nov. 05, 2002
Tetsuichiro Ichiguchi, Hyogo, JP;
Tsutomu Nagasawa, Hyogo, JP;
Tadaaki Yamauchi, Hyogo, JP;
Zengcheng Tian, Hyogo, JP;
Makoto Suwa, Hyogo, JP;
Junko Matsumoto, Hyogo, JP;
Takeo Okamoto, Hyogo, JP;
Hideki Yonetani, Hyogo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.