The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6721232 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 13, 2004

Filed:

Jun. 18, 2002
Applicant:
Inventor:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.


Find Patent Forward Citations

Kashiwazaki, Yasuhiro. (2004). Semiconductor device having phase error improved dll circuit mounted thereon (U.S. Patent No. 6721232). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6721232

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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