The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2004

Filed:

Mar. 16, 2001
Applicant:
Inventors:

Richard Ronald Hall, Endwell, NY (US);

How Tzu Lin, Vestal, NY (US);

Christopher John Majka, Owego, NY (US);

Norman Corey Seastrand, Apalachin, NY (US);

Matthew Francis Seward, Windsor, NY (US);

Ronald Verne Smith, Friendsville, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/02 ; H05K 7/06 ; H05K 7/08 ; H05K 7/10 ;
U.S. Cl.
CPC ...
H05K 7/02 ; H05K 7/06 ; H05K 7/08 ; H05K 7/10 ;
Abstract

A multi-layer electronic structure includes an increased capacity for the attachment of active or passive devices thereto. This is achieved by creating a three-dimensional grid of connection points to electrically couple active or passive surface mounted devices to edge mounted devices. The grid pattern is useful with any laminate including circuit cards, ceramic modules and flexible circuits. The variety of electrical devices that may be connected to the cross-sectional substrate includes, but is not limited to, chips such as semiconductor chips, diodes, resistors, capacitors and printed wiring boards. The structure can be used to more rapidly pass data, such as optical data that is transmitted from a spectroscope through a VCSEL laser and the electronic structure to a computer for diagnostics and analysis. A stepped arrangement of circuitized laminates is described for this purpose.


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