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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6718440 B1

PDFFull Text
Date of Patent:
Apr. 06, 2004

Filed:

Sep. 28, 2001

Memory access latency hiding with hint buffer

Applicant:
Inventors:

Subramaniam Maiyuran, Gold River, CA (US);

Vivek Garg, Folsom, CA (US);

Mohammad A. Abdallah, Folsom, CA (US);

Jagannath Keshava, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Blakely, Sokoloff, Taylor & Zafman LLP

Primary Examiner:

Matthew Kim

Assistant Examiner:

Stephen Elmore

Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

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Maiyuran, Subramaniam. (2004). Memory access latency hiding with hint buffer (U.S. Patent No. 6718440). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6718440

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