The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6716559 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 06, 2004

Filed:

Dec. 13, 2001
Applicant:
Inventors:

Robert K. Leidy, Burlington, VT (US);

Timothy C. Milmore, South Burlington, VT (US);

Matthew C. Nicholls, South Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 ;
U.S. Cl.
CPC ...
G03F 9/00 ;
Abstract

A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.


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