The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6715105 B1

Date of Patent:

Mar. 30, 2004

Filed:

Nov. 14, 2000

Method for reducing stored patterns for ic test by embedding built-in-self-test circuitry for chip logic into a scan test access port

Applicant:

Inventor:

Jeff Rearick, Ft Collins, CO (US);

Assignee:

Agilent Technologies, Inc., Palo Alto, CA (US);

Attorney:

Primary Examiner:

Scott Baderman

Assistant Examiner:

Anne L Damiano

Int. Cl.

CPC ...

G01R 3/128 ;

U.S. Cl.

CPC ...

G01R 3/128 ;

Abstract

A test method and apparatus allows simultaneous loading of multiple scan chains via a single common scan-in port (SDI) and a scan clock signal SCAN CLOCK. Data is scanned into one or more scanpaths from a scan data in (SDI) port under the control of a clock signal, either directly or indirectly through a linear feedback shift register (LFSR). Scan-out data output from the scanpaths may be read at the scan data out (SDO) port, either directly or indirectly through a signature register with optional masking functionality.

Find Patent Forward Citations

Rearick, Jeff. (2004). Method for reducing stored patterns for ic test by embedding built-in-self-test circuitry for chip logic into a scan test access port (U.S. Patent No. 6715105). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6715105

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