Lock detector and phase locked loop circuit

Abstract

There are provided a lock detector that does not output a lock detecting signal of incorrect content even when approaching phase synchronization, when an input signal stops suddenly, or when a phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector. Specifically, a PLL circuit includes a lock detector ( ) which comprises a reset signal output part ( to ) that outputs a reset signal (Pe) upon a phase difference between an input signal (f ) and a feedback signal (f ); and a D-FF circuit ( ) that does not output a lock detecting signal (SL) upon receipt of the reset signal. The feedback signal (f ) is inputted to an NAND circuit ( ) such that the reset signal is also based on the signal change of the feedback signal (f ). Further, a counter ( ) performing output when the input signal (f ) reaches N-cycle is used for the clock of the D-FF circuit ( ).