The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6713782 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 30, 2004

Filed:

Nov. 13, 2002
Applicant:
Inventor:

Kuo-Chun Wu, San Jose, CA (US);

Assignee:

Mosel Vitelic, Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/358 ;
U.S. Cl.
CPC ...
H01L 2/358 ;
Abstract

In fabrication of integrated circuits, trenches ( ) are formed in a dielectric ( ), then a metal (e.g. tungsten or copper) is deposited. The metal ( ) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure ( ) can be estimated by measuring the erosion of a smaller test structure ( ). The erosion of the test structure is measured by a probe instrument ( ), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.


Find Patent Forward Citations

Wu, Kuo-Chun. (2004). Polishing of conductive layers in fabrication of integrated circuits (U.S. Patent No. 6713782). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6713782

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