The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2004
Filed:
Jan. 18, 2002
Alexander L. Barr, Austin, TX (US);
Suresh Venkatesan, Austin, TX (US);
David B. Clegg, Austin, TX (US);
Rebecca G. Cole, Austin, TX (US);
Olubunmi Adetutu, Austin, TX (US);
Stuart E. Greer, Austin, TX (US);
Brian G. Anthony, Austin, TX (US);
Ramnath Venkatraman, Austin, TX (US);
Gregor Braeckelmann, Austin, TX (US);
Douglas M. Reber, Austin, TX (US);
Stephen R. Crown, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An interconnect overlies a semiconductor device substrate ( ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( ) overlies the conductive barrier layer and the passivation layer ( ) has an opening that exposes portions of the conductive barrier layer ( ). In an alternate embodiment a passivation layer ( ) overlies the interconnect, the passivation layer ( ) has an opening ( ) that exposes the interconnect and a conductive barrier layer ( ) overlies the interconnect within the opening ( ).