Methods and apparatus for increasing data bandwidth in a dynamic memory device by generating a delayed address transition detection signal in response to a column address strobe signal

Abstract

The present invention includes a cost efficient method of substantially increasing the data bandwidth of a dynamic random access memory (DRAM) device initially configured to operate in an extended data output (EDO) mode, the EDO DRAM device including at least one storage cell, a column decoder, an internal read/write data bus and an off chip driver latch, the column decoder decoding a column address upon receipt thereof such that data stored in the at least one storage cell corresponding to the decoded column addresses is placed on the internal read/write data bus in response to the receipt of an address transition detection (ATD) pulse generated by the dynamic memory device and further wherein output data is stored in the off chip driver latch in response to a transfer pulse. The method includes the steps of temporarily suppressing the generation of the ATD pulse such that data selected from the at least one storage cell is not placed on internal read/write data bus until after a delayed generation of the ATD pulse in response to the falling edge of a column address strobe (CAS) signal, such that a first pipeline stage is thereby substantially defined.