The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2004

Filed:

Jul. 19, 2002
Applicant:
Inventors:

Toru Tanzawa, Ebina, JP;

Tadayuki Taura, Zushi, JP;

Masao Kuriyama, Fujisawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A potential generating circuit generates two types of erase verify threshold values EVT and EVT . These values satisfy the relationship of EVT =EVT +(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT , the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT and is lower than OEVT. The erase verify threshold values EVT and EVT are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT . On the other hand, during the normal operation, the erase verify threshold value is set at EVT


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