The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2004
Filed:
Oct. 03, 2002
Anders T. Dejenfelt, Palo Alto, CA (US);
David Kuan-Yu Liu, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An EEPROM memory cell array architecture ( ) that substantially eliminates leakage current to allow for reading memory cells ( ) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor ( ). On one embodiment, the ground transistor ( ) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor ( ) and the memory cell=s read transistor ( ). In another embodiment, the ground transistor ( ) is a low voltage transistor controlled by a separate low voltage control signal.