Distributed power device with dual function minority carrier reduction

Abstract

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region ( ) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.