Fabrication of semiconductor devices having high-voltage mos transistors and low-voltage mos transistors

Abstract

Methods of fabricating a semiconductor device having low-voltage MOS transistors and high-voltage metal-oxide semiconductor (“MOS”) transistors are provided. The method includes forming a device isolation layer at a predetermined region of a semiconductor substrate. The device isolation layer defines first and second active regions in low and high-voltage MOS transistor regions, respectively. A capping layer pattern is formed to cover the low-voltage MOS transistor region. The capping layer pattern exposes the second active region in the high-voltage MOS transistor region. A first gate oxide layer is formed on an entire surface of the semiconductor substrate having the capping layer pattern. The first gate oxide layer is formed using a chemical vapor deposition (“CVD”) technique. The first gate oxide layer serves as a gate insulating layer of the high-voltage MOS transistor. The first gate oxide layer in the low-voltage MOS transistor region and the capping layer pattern are then etched to expose the first active region. A second gate oxide layer is formed using a thermal oxidation technique on the first active region. The second gate oxide layer is formed to a thickness, which is thinner than the first gate oxide layer. The second gate oxide layer serves as a gate insulating layer of the low-voltage MOS transistor.