Generation of margining voltage on-chip during testing cam portion of flash memory device

Abstract

For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer. In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source for erase margining of the CAM cell.