The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2004
Filed:
Jan. 28, 2003
Takashi Suzuki, Kawasaki, JP;
Satoshi Otsuka, Kawasaki, JP;
Tsutomu Hosoda, Kawasaki, JP;
Hirofumi Watatani, Kawasaki, JP;
Shun-ichi Fukuyama, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor device has: a semiconductor substrate; a number of semiconductor elements formed on the semiconductor substrate; a plurality of lower level wiring layers electrically connected to the semiconductor elements; a plurality of first insulating layers electrically separating the lower level wiring layers and having a first dielectric constant; a plurality of middle level wiring layers electrically connected to the lower level wiring layers; a plurality of second insulating layers electrically separating the middle level wiring layers and having a second dielectric constant larger than the first dielectric constant; a plurality of upper level wiring layers electrically connected to the middle level wiring layers; a plurality of third insulating layers electrically separating the upper level wiring layers and having a third dielectric constant larger than the second dielectric constant. A multilevel wiring structure is provided which has a high performance and a high reliability.