The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2004
Filed:
Jan. 17, 2003
Che-yu Li, Ithaca, NY (US);
Sharon Laura Moriarty, Mountain View, CA (US);
Zhineng Fan, Santa Clara, CA (US);
High Connection Density, Inc., Sunnyvale, CA (US);
Abstract
The present invention is a family of memory modules. In one embodiment a memory module with granularity and upgradeability of bandwidth, and a low profile uses 256 MB SDRAM or DDR SDRAM memory devices in chip scale packages (CSPs) to support a memory data bus width of up to at least 512 bits. Each module includes an impedance-controlled substrate having contact pads, memory devices, and other components on its surfaces. In one embodiment, the inclusion of spaced apart multiple area array interconnections allows a row of memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating matching of interconnect lengths. Short area array interconnections, including ball grid array (BGA) and land grid array (LGA) options, provide electrical communication between modules and the rest of the system. Thermal control structures may be included to maintain reliable operating temperatures.