The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2004
Filed:
Jul. 16, 2002
Koichi Nishida, Tenri, JP;
Kazuhisa Okada, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.