Unified timing analysis for model interface layout parasitics

Abstract

A modeling method to improve the accuracy of timing analysis that more closely models timing information associated with layout parasitics that are connected to interface pins of a transistor-level subcircuit. A method is described for performing a hierarchical timing analysis of a circuit having a transistor-level subcircuit. Certain data (e.g., the layout parasitic data associated with interface nodes) associated with the transistor-level subcircuit are set aside. A timing model (timing arcs) of the transistor-level subcircuit is created without using these data. The timing analysis of the circuit is performed using a circuit analyzer. The circuit analyzer uses the timing model (timing arcs) and the layout parasitic data for the transistor-level subcircuit in the timing analysis. Thus, the layout parasitic data associated with the lower level subcircuit is preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.