The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2004
Filed:
Aug. 20, 2002
Applicant:
Inventors:
Assignee:
Renesas Technology Corp., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract
During a burn-in test, each read selection gate, each write selection gate, a write control circuit, and a sense amplifier circuit are activated, and a read data bus precharge and equalize circuit and a global read data bus precharge and equalize circuit are inactivated. As a result, a voltage difference applied between a global write data bus pair is transferred to each of a write data bus pair, a bit line pair, a read data bus pair, and a global read data bus pair without involving a mode switching.
Izutsu, Takashi. (2004). Semiconductor memory device including data bus pairs respectively dedicated to data writing and data reading (U.S. Patent No. 6704238). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6704238
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile