Sense amplifier bias circuit for a memory having at least two distinct resistance states

Abstract

In a memory, a bias circuit ( ) uses a current reference ( ) for providing a reference current and control circuitry ( ) to bias a sense amplifier ( ) with a varying voltage (V ). The varying voltage maintains current through MRAM bit cells ( ) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier ( ) and mock array of bit cells ( ) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.