The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2004

Filed:

Aug. 05, 2002
Applicant:
Inventors:

Senol Pekin, San Jose, CA (US);

Anand Govind, San Jose, CA (US);

Carl Iwashita, San Carlos, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/348 ;
Abstract

A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.


Find Patent Forward Citations

Pekin, Senol. (2004). Flip-chip ball grid array package for electromigration testing (U.S. Patent No. 6700207). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6700207

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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